This application claims the benefit of the priority date of Korean Patent Application No. 2002-09323, filed Feb. 21, 2002 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for manufacturing a flash memory.
2. Description of the Related Art
Flash memory devices are commonly constructed with double gates including a floating gate and a control gate. In this manner, data is memorized (i.e. stored) or removed (I.e. read) when a voltage is applied to the double gates. In particular, cooperation between the floating gate and the control gate greatly affects the speed and reliability of a memory, and thus techniques for manufacture of the floating gate and the control gate are under constant development.
FIG. 13 is a cross sectional view of a conventional flash memory device having a control gate and the floating gate.
Referring to FIG. 13, the conventional flash memory device includes a plurality of control gates 1230, a source junction 1201, a drain junction 1101, a junction contact fill 1210 and at least two floating gates 1120. The plurality of control gates 1230 are aligned linearly. The source junction 1201 is interposed between the control gates 1230 and is formed on a semiconductor substrate 1100. The drain junction 1101 is disposed at both sides of the control gates 1230 and is formed on the semiconductor substrate 1100. The junction contact fill 1210, at both sides of which the control gates 1230 are formed and inner insulating film spacers 1190 are interposed between the control gates 1230, connects a source junction 1201 to interconnections of an upper portion of the contact.
The floating gate 1120 is interposed between a sidewall of the control gate 1230 and a second gate insulating film 1220, and is also interposed between a sidewall of the control gate 1230 and a first gate insulating film 1110 under the second gate insulating film 1220, and partially overlaps with the source junction 1201 of the semiconductor substrate 1100. Outer insulating film spacers 1260 are formed on outer sidewalls of the control gate 1230. Here, inner insulating film spacers 1190 are formed on the inner sidewalls of the control gate 1230, burying the floating gate 1120. A predetermined contact hole (not shown) is formed between inner insulating film spacers 1190 which face each other. The junction contact fill 1210 is formed of a conductive film to cover the predetermined contact and thus connects interconnections (not shown) of the upper portion and the source junction 1201. Here, the control gate 1230 and the floating gate 1120 are formed of doped polysilicon.
In the conventional flash memory device, the second gate insulating film 1220 is formed on the floating gate 1120, and thus it functions as a switch between the floating gate 1120 and the control gate 1230. If a potential difference occurs, charges move, and thus information may be memorized or removed.
However, in the conventional flash memory, the second gate insulating film 1220 is formed by oxidizing polysilicon and has an uneven surface, a fact which makes it difficult to uniformly form the second gate insulating film 1220 or floating gate 1120. Thus, on/off operations between the floating gate 1120 and the control gate 1230 are not executed stably. In particular, the second gate insulating film 1220 in the region in contact both the control gate 1230 and the floating gate 1120 is thick and not uniform, and thus an error can occur when erasing data from the memory device.
It is an object of the present invention to provide a semiconductor memory device that can facilitate an erase operation by forming a sharp region between a first gate, i.e., a floating gate, and a second gate, i.e., a control gate, of a flash memory device and making smooth movement of charges possible during an erase operation.
According to a first embodiment of the present invention, there is provided a method for manufacturing a flash memory device comprising (a) sequentially forming a first gate insulating film, a first gate conductive film, and a second insulating film on a semiconductor substrate, (b) defining a region for a first gate by etching part of the second insulating film to expose an upper portion of the first gate conductive film, (c) forming second conductive film spacers along sidewalls of the patterned second insulating film, (d) forming an oxide film on the exposed surface of the second conductive film spacers and the first gate conductive film, (e) forming silicon insulating spacers on sidewalls of the etched second insulating film, (f) forming a source junction contact hole by etching the first gate conductive film and the first gate insulating film, using the second insulating film and the silicon insulating film spacers as an etch mask, (g) forming a source junction contact fill by filling the source junction contact hole with conductive film, (h) forming the first gate by sequentially removing the second insulating film and the first gate conductive film beneath the second insulating film, (i) forming a second gate insulating film on an exposed sidewall of the first gate, (j) exposing upper portions of the source junction contact fill and the second gate conductive film by sequentially forming a second gate conductive film and a silicon nitride film on the semiconductor substrate and removing the silicon nitride film so that it is level with an upper portion of the insulating spacers, (k) forming a mask silicon oxide layer over the exposed source junction contact fill and the second gate conductive film and (l) forming a second gate by sequentially removing the exposed silicon nitride film and the second gate conductive film under the silicon nitride film.
Here, the first gate conductive film is formed of conductive polysilicon, and the second insulating film is formed of silicon nitride.
In step (c), a conductive polysilicon is formed on the semiconductor substrate. Then, the conductive polysilicon is etched in an anisotropic dry etching process, and thus the polysilicon spacer is formed in the lower portion of the sidewall of the mask insulating film. The silicon oxide film of step (d) is formed by oxidizing the exposed first gate conductive film and the second conductive film spacers.
In step (e), a silicon insulating film is formed on the entire semiconductor substrate and the silicon insulating film is anisotropically etched by dry etching. Then, the silicon insulating spacers is formed in the sidewall of the etched silicon nitride film.
After that, the polysilicon of the first gate conductive film and the first gate insulating film are removed by dry etching, and a source junction contact hole is formed. Preferably, the silicon oxide film is formed by chemical vapor deposition CVD.
In order to form the source junction contact fill, a doped polysilicon is deposited as a filling conductive film by low pressure chemical vapor deposition LPCVD on the entire semiconductor substrate. Then, the filling conductive film formed of the polysilicon is removed by chemical mechanical polishing, and thus the source junction contact fill is formed between grooves of the gate pattern.
The sidewall of the first gate conductive film is exposed by removing the second insulating film formed of the silicon nitride by wet etching using a phosphoric acid (H3PO4) solution. A second gate insulating film is formed on the exposed sidewall of the first gate insulating film. Here, the second gate insulating film may be formed by two methods. Firstly, it may be formed by oxidizing the sidewall of the first gate conductive film of the polysilicon by dry oxidation or wet oxidation. Secondly, it may be formed like a spacer by forming a silicon oxide film to an appropriate thickness by CVD and a spacer etching of the silicon oxide film by anisotropic etching.
A polysilicon as the second gate conductive film and a silicon insulating film are sequentially formed on the entire semiconductor substrate. The silicon insulating film and the second gate conductive film are sequentially removed by chemical mechanical polishing to expose the source junction contact fill. Here, the silicon insulating film is a silicon nitride film.
A mask silicon oxide film is formed by oxidizing the source junction contact fill and the exposed portion of the second gate conductive film by dry oxidation or wet oxidation. The silicon insulating film and the second gate conductive film are removed by dry etching using the silicon oxide film as a mask, and thus a second gate pattern is formed on the second gate conductive film.
It is preferable that the second gate conductive film is formed of a combination of doped polysilicon and undoped polysilicon on the doped polysilicon, so as to make the oxide film thin when the oxide film is formed by oxidizing the exposed polysilicon.
As described above, according to the present invention, the sharp region where the first conductive film contacts the second gate conductive film is formed by oxidizing the first gate conductive film formed of the floating gate, and thus charges are concentrated in the sharp region, such that electronic data can be readily stored or erased.